PROSAGA码农传奇-FPGA/ASIC-基于4位加法器的VHDL 4位乘法器

<div class =“post-text”itemprop =“text”>
  
    
      “我被困在港口地图上”
    
     不是具体的问题陈述。
  
  
    通过命名关联，可以关联地图中正式端口的成员
    
      个别地
    
     以及在...
    
      整个
    
     只要正式的所有成员都相关联 - IEEE Std 1076-2008 6.5.7协会列表：
  
  <BLOCKQUOTE>
    
      正式的接口对象应该是显式声明的接口对象或这种接口对象的成员（见5.1）。在前一种情况下，这样的形式据说是
      
        完全相关的
      
      。在后一种情况下，应使用命名关联将正式和实际联系起来;据说这种正式的子元素是
      
        单独关联
      
      。此外，显式声明的接口对象的每个标量子元素应与同一关联列表中的实际（或其子元素）恰好相关联一次，并且所有这些关联应出现在该关联列表内的连续序列中。与接口对象的切片或子元素（或其片）相关联的每个关联元素应使用本地静态名称来标识形式。
    
  </BLOCKQUOTE>
  
    注意你有太多的进位元素（只需要两个），不需要和（0），不需要sumout（0），sumout（4）或sumout（11 downo 8），multy中有一个无关的字符架构，你缺少上下文条款，并有未使用的使用条款。
  
  
    使用数组中间信号的代码：
  
   <pre>
 <code>
 library ieee;
use ieee.std_logic_1164.all;
-- use ieee.std_logic_textio.all; -- NOT USED
-- use ieee.std_logic_unsigned.all; -- NOT USED

entity multy is 
    port (
        x: in  std_logic_vector (3 downto 0);
        y: in  std_logic_vector (3 downto 0);
        p: out std_logic_vector (7 downto 0)
    );
end entity multy;

architecture rtl of multy is
    component Ripple_Adder
        port ( 
            A:      in  std_logic_vector (3 downto 0);
            B:      in  std_logic_vector (3 downto 0);
            Cin:    in  std_logic;
            S:      out std_logic_vector (3 downto 0);
           Cout:    out std_logic
        );
    end component;
-- AND Product terms:
    signal G0, G1, G2:  std_logic_vector (3 downto 0);
-- B Inputs (B0 has three bits of AND product)
    signal B0, B1, B2:  std_logic_vector (3 downto 0);

begin

-- y(1) thru y (3) AND products, assigned aggregates:
 G0 <= (x(3) and y(1), x(2) and y(1), x(1) and y(1), x(0) and y(1));
 G1 <= (x(3) and y(2), x(2) and y(2), x(1) and y(2), x(0) and y(2));
 G2 <= (x(3) and y(3), x(2) and y(3), x(1) and y(3), x(0) and y(3));
 -- y(0) AND products (and y0(3) '0'):
 B0 <= ('0', x(3) and y(0), x(2) and y(0), x(1) and y(0));

-- named association:
cell_1: 
 Ripple_Adder 
 port map (
 a => G0,
 b => B0,
 cin => '0',
 cout => B1(3), -- named association can be in any order
 S(3) => B1(2), -- individual elements of S, all are associated
 S(2) => B1(1), -- all formal members must be provide contiguously
 S(1) => B1(0),
 S(0) => p(1)
 );
cell_2: 
 Ripple_Adder 
 port map (
 a => G1,
 b => B1,
 cin => '0',
 cout => B2(3),
 S(3) => B2(2),
 S(2) => B2(1),
 S(1) => B2(0),
 S(0) => p(2)
 );
cell_3: 
 Ripple_Adder 
 port map (
 a => G2,
 b => B2,
 cin => '0',
 cout => p(7),
 S => p(6 downto 3) -- matching elements for formal
 );
 p(0) <= x(0) and y(0); 
end architecture rtl;

</code>
 </pre>
  
    借用测试平台来演示：
  
   <pre>
 <code>
 library ieee;
use ieee.std_logic_1164.all;

entity multy_tb is           -- testbench
end entity;

architecture foo of multy_tb is
    signal x, y:        std_logic_vector (3 downto 0);
    signal yp, rp:      std_logic_vector (7 downto 0);

use ieee.numeric_std.all;

function to_string (inp: std_logic_vector) return string is
        variable image_str: string (1 to inp'length);
        alias input_str:  std_logic_vector (1 to inp'length) is inp;
    begin
        for i in input_str'range loop
            image_str(i) := character'VALUE(std_ulogic'IMAGE(input_str(i)));
        end loop;
        return image_str;
    end function;

begin
DUT:
 entity work.multy
 port map (
 x => x,
 y => y,
 p => yp
 );
STIMULI:
 process
 begin
 for i in 0 to 15 loop
 x <= std_logic_vector(to_unsigned(i, x'length));
 for j in 0 to 15 loop
 y <= std_logic_vector(to_unsigned(j, y'length));
 wait for 0 ns; -- assignments take effect
 rp <= std_logic_vector(unsigned (x) * unsigned(y));
 wait for 10 ns;
 if yp /= rp then
 report "multy error";
 report HT & "expected " & to_string (rp);
 report HT & "got " & to_string (yp);
 end if;
 end loop;
 end loop;
 wait;
 end process;
end architecture;

</code>
 </pre>
  
    for_string函数包含在pre-2008模拟器中。上下文子句被添加到FA和Ripple_Adder。
  
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