Redesigned the RNBIP single-bus architecture to implement a 3 stage instruction-level pipeline.
Basic 8-bit microprocessor.
3-stage Pipeline:
The letter on the top left corner in each register denotes the cycle in which it is updated.
Fetch: In the fetch stage, the opcode and operand are read from the program memory, addressed by the program counter. The opcode is stored in the Instruction Register (IR) and operand is stored in the Operand Register 1 (OR1).
Read: The operand is buffered and copied into OR2 from OR1. Simultaneously, OR1 gets loaded with a new value of the operand, coming from the next fetch cycle.
Execute: The register values are read, ALU/data memory operations take place and any the registers are updated if needed. In case of a branch the program counter and stack pointer are updated as necessary.
More details about the implemented architecture are present in the doc folder.
The code is present in the src folder.