项目作者: lakshmi-sathi

项目描述 :
8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x multiplied clock at ~50% duty cycle on tt corner at room temperature.
高级语言:
项目地址: git://github.com/lakshmi-sathi/avsdpll_1v8.git
创建时间: 2020-10-28T00:13:31Z
项目社区:https://github.com/lakshmi-sathi/avsdpll_1v8

开源协议:GNU General Public License v2.0

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