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项目作者： 8bitgeek

项目描述 ：
Board Support for BRISCITS: Basic RISC Intrinsic Time Scheduler | Lightweight preemtive multi-tasking for RISC-V micro-controllers.
高级语言： C
项目地址: git://github.com/8bitgeek/briscits-bsp.git
创建时间： 2021-07-20T18:10:58Z
项目社区：https://github.com/8bitgeek/briscits-bsp
开源协议：
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NOTE REPOSITORY HAS MOVED

REPOSITORY URL: https://bitbucket.org/8bitgeek/briscits-bsp

  1.  ________  ________  ___  ________  ________  ___  _________  ________      
  2. |\   __  \|\   __  \|\  \|\   ____\|\   ____\|\  \|\___   ___\\   ____\     
  3. \ \  \|\ /\ \  \|\  \ \  \ \  \___|\ \  \___|\ \  \|___ \  \_\ \  \___|_    
  4.  \ \   __  \ \   _  _\ \  \ \_____  \ \  \    \ \  \   \ \  \ \ \_____  \   
  5.   \ \  \|\  \ \  \\  \\ \  \|____|\  \ \  \____\ \  \   \ \  \ \|____|\  \  
  6.    \ \_______\ \__\\ _\\ \__\____\_\  \ \_______\ \__\   \ \__\  ____\_\  \ 
  7.     \|_______|\|__|\|__|\|__|\_________\|_______|\|__|    \|__| |\_________\
  8.                             \|_________|                        \|_________|
  9.       BOARD SUPPORT

BRISCITS

This is a Board Support project for BRISCITS.

Prerequisite

RISCV OpenOCD

Git Repository

https://github.com/riscv/riscv-openocd

Pre-compiled binary for 64-bit ARM (aarch64) Linux Host

riscv-openod-0.00.0-aarch64.tar.gz

RISCV GCC

Git Repository

https://github.com/riscv/riscv-gnu-toolchain

Pre-compiled binary for 64-bit ARM (aarch64) Linux Host

./configure --prefix=/opt/riscv --with-arch=rv32i --with-abi=ilp32 --enable-multilib

riscv32-unknown-elf-gcc-aarch64-11.1.0.tar.gz

Initialize

  1. git clone https://github.com/8bitgeek/briscits-bsp.git
  2. cd briscits-bsp
  3. git submodule init
  4. git submodule update

Environment Setup

Prior to compiling for a particular CPU target, some environment variables need to be set up.

  • BRISC_CPU should reference one of the CPU support packages under the cpu/ folder.
  • BRISC_GCC should contain the ‘gcc’ compiler prefix.
  • BRISC_CFLAGS should contains compiler flags for instance “-ggdb” or “-Os”

RISC-V

  1. export BRISC_CPU=riscv/BumbleBee/RV32IMAC
  2. export BRISC_GCC=riscv32-unknown-elf
  1. export BRISC_CPU=riscv/Qingke/RV32IMAC
  2. export BRISC_GCC=riscv32-unknown-elf

Cortex-M7

  1. export BRISC_CPU=arm/cortex-m7
  2. export BRISC_GCC=arm-none-eabi

Debug

  1. export BRISC_CFLAGS=-ggdb

Release

  1. export BRISC_CFLAGS=-Os

Make BRISCITS scheduler (libbrisc.a)

  1. cd briscits
  2. make
  3. cd ..

SiPEED Longan Nano (GD32VF103CBT6) 32-bit RISCV BumbleBee RV32IMAC

  1. make -f bsp/sipeed-longan-nano/Makefile

WaveShare (STM332F746) 32-bit Cortex-M7

  1. make -f bsp/generic-stm32f746/Makefile

OpenOCD RISCV

Using PINE64 USB JTAG with GD32VF103 MCU and GDB

  1. /opt/riscv-openocd/bin/openocd -c "adapter speed 1000" \
  2.     -f /opt/riscv-openocd/share/openocd/scripts/interface/ftdi/um232h.cfg \
  3.     -f /opt/riscv-openocd/share/openocd/scripts/target/gd32vf103.cfg

Attach GDB on RISCV target

  1. riscv-unknown-elf-gdb ./main.elf
  2. target extended-remote localhost:3333
  3. load main.elf
  4. break main
  5. continue

….or….

  1. riscv-unknown-elf-gdb -x scripts/gdbinit

Flash GD32VF103 MCU

  1. /opt/riscv-openocd/bin/openocd -c "adapter speed 1000" \
  2.     -f /opt/riscv-openocd/share/openocd/scripts/interface/ftdi/um232h.cfg \
  3.     -f /opt/riscv-openocd/share/openocd/scripts/target/gd32vf103.cfg \
  4.     -c "program main.elf verify reset exit"