项目作者: jkiv

项目描述 :
FPGA core for SHA256d mining targeting Lattice iCE40 devices.
高级语言: Verilog
项目地址: git://github.com/jkiv/shapool-core.git
创建时间: 2018-05-04T18:02:27Z
项目社区:https://github.com/jkiv/shapool-core

开源协议:BSD 3-Clause "New" or "Revised" License

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