项目描述 ：
In this type of register, there are no interconnections between the individual flip-flops since no serial shifting of the data is required. Data is given as input separately for each flip flop and in the same way, output also collected individually from each flip flop.

高级语言： Verilog

项目主页：

项目地址: git://github.com/mnmhdanas/Parallel-IN-Parallel-OUT.git

创建时间： 2021-07-24T15:56:28Z
项目社区：https://github.com/mnmhdanas/Parallel-IN-Parallel-OUT
开源协议：
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