项目描述 ：
In this shift register, we can apply the parallel inputs to each D flip-flop by making Preset Enable to 1. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we will get the serial output from the right most D flip-flop.

高级语言： Verilog

项目主页：

项目地址: git://github.com/mnmhdanas/Parallel-IN-Serial-OUT.git

创建时间： 2021-07-24T15:52:51Z
项目社区：https://github.com/mnmhdanas/Parallel-IN-Serial-OUT
开源协议：
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