项目描述 ：
In this shift register, we can send the bits serially from the input of left most D flip-flop. Hence, this input is also called as serial input. For every positive edge triggering of clock signal, the data shifts from one stage to the next. So, we can receive the bits serially from the output of right most D flip-flop. Hence, this output is also called as serial output.

高级语言： Verilog

项目主页：

项目地址: git://github.com/mnmhdanas/Serial-IN-Serial-OUT.git

创建时间： 2021-07-24T15:45:13Z
项目社区：https://github.com/mnmhdanas/Serial-IN-Serial-OUT
开源协议：
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