项目描述 ：
SPI is a synchronous, full duplex master-slave-based interface. The data from the master or the slave is synchronized on the rising or falling clock edge based on mode .Both master and slave can transmit data at the same time. The SPI interface got 4 wires.

高级语言： Verilog

项目主页：

项目地址: git://github.com/mnmhdanas/SPI-protocol.git

创建时间： 2021-07-27T15:08:14Z
项目社区：https://github.com/mnmhdanas/SPI-protocol
开源协议：
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