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项目作者： NosherwanA

项目描述 ：
Stopwatch implementation on a Cyclone V FPGA
高级语言： VHDL
项目地址: git://github.com/NosherwanA/Stopwatch.git
创建时间： 2017-12-17T15:41:25Z
项目社区：https://github.com/NosherwanA/Stopwatch
开源协议：MIT License
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Stopwatch

Implementation of a stopwatch, accurate to a 100th of a second, on an Altera Cyclone 5 FPGA

Components

  1. 100Hz Clock divider
  2. Counter
  3. Hex Display module

Future Improvements

  • Adding lap time functionality
  • Implementing a countdown timer
  • Eventually, combining stopwatch, countdown timer functionaily with a 24 hour time to emulate an everyday clock

License

This project is licensed under the MIT License - see the LICENSE.md file for details