项目描述 ：
Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.

高级语言： Verilog

项目主页：

项目地址: git://github.com/gabrielganzer/RTL-PowerOptimization.git

创建时间： 2020-06-27T13:02:06Z
项目社区：https://github.com/gabrielganzer/RTL-PowerOptimization
开源协议：BSD 3-Clause "New" or "Revised" License
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