项目作者： hidrogencloride
项目描述 ：
Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench.
高级语言： SystemVerilog
项目地址: git://github.com/hidrogencloride/verilog-halfAdder.git
verilog-halfAdder
Hardware Simulation using Icarus Verilog EDA Playground for a half adder circuit design and test bench.
By definition, a half adder is a digital circuit that receives two (one bit binary) inputs A and B, and outputs both their sum and carry.
