Slaves for AXI-lite interface
This repository contains simple AXI-Lite slaves for GPIOs of some FPGA boards as well as a generic AXI-Lite slave.
Gives access to the basic GPIO ports (seven segment display, buttons, switches and LEDs) of the Digilent Basys 3 FPGA board. Register mapping can be changed via GUI or parameters. Included driver will work regardless of the mapping.
| Name | Default Offset | Access | Description |
|---|---|---|---|
| Config | 0x00 | R/W | Configurations for IP |
| led | 0x04 | R/W | LEDs |
| sw | 0x08 | R | Switches |
| ssd | 0x0C | R/W | Seven Segment Display |
| btn all | 0x10 | R | Combined Button Counter |
| btnL | 0x14 | R | Left Button Counter |
| btnU | 0x18 | R | Up Button Counter |
| btnR | 0x1C | R | Right Button Counter |
| btnD | 0x20 | R | Down Button Counter |
Configuration Register:
| 31:6 | 5:2 | 1 | 0 |
|:—-:|:—-:|:—-:|:—-:|
|Reserved |Enable digits|Overwrite SSD config.|Keep Button Values|
Combined Button Counter:
| 31:24 | 23:16 | 15:8 | 7:0 |
|:—-:|:—-:|:—-:|:—-:|
|Left Button|Up Button|Right Button|Down Button|
Last Simulation: 18 October 2021, with Vivado Simulator.
Last Test: 09 October 2021, on Digilent Basys 3.
Gives access to the basic GPIO ports (buttons, switches and LEDs) of the Digilent Arty A7 FPGA board. Register mapping can be changed via GUI or parameters. Included driver will work regardless of the mapping.
| Name | Default Offset | Access | Description |
|---|---|---|---|
| Config | 0x00 | R/W | Configurations for IP |
| PWM led | 0x04 | R/W | Phase Width Modulated LED control |
| Toggle led | 0x08 | R/W | Toggle LED control |
| sw | 0x0C | R | Switches |
| rgb0 | 0x10 | R/W | RGB LED 0 |
| rgb1 | 0x14 | R/W | RGB LED 1 |
| rgb2 | 0x18 | R/W | RGB LED 2 |
| rgb3 | 0x1C | R/W | RGB LED 3 |
| btn0 | 0x20 | R | Button 0 Counter |
| btn1 | 0x24 | R | Button 1 Counter |
| btn2 | 0x28 | R | Button 2 Counter |
| btn3 | 0x2C | R | Button 3 Counter |
| btn all | 0x30 | R | Combined Button Counter |
Configuration Register:
| 31:10 | 9:2 | 1 | 0 |
|:—-:|:—-:|:—-:|:—-:|
|Reserved |Toggle Brightness|Enable Toggle Mode|Keep Button Values|
In combined registers, GPIO with higher number has higher address.
Last Simulation: 18 October 2021, with Vivado Simulator.
Last Test: 10 October 2021, on Digilent Arty A7.
Gives access to the basic GPIO ports (buttons, switches and LEDs) of the Digilent Nexys Video FPGA board. Register mapping can be changed via GUI or parameters. Included driver will work regardless of the mapping.
| Name | Default Offset | Access | Description |
|---|---|---|---|
| Config | 0x00 | R/W | Configurations for IP |
| led | 0x04 | R/W | LEDs |
| sw | 0x08 | R | Switches |
| btnC | 0x0C | R | Center Button Counter |
| btnD | 0x10 | R | Down Button Counter |
| btnL | 0x14 | R | Left Button Counter |
| btnU | 0x18 | R | Up Button Counter |
| btnR | 0x1C | R | Right Button Counter |
Configuration Register:
| 31:1 | 0 |
|:—-:|:—-:|
|Reserved|Keep Button Values|
Last Simulation: 10 October 2021, with Vivado Simulator.
Last Test: 10 October 2021, on Digilent Nexys Video.
This IP provides a simpler interface for AXI4-Lite protocol. IP handles all signalling for AXI lite interface with a simpler interface with only two channels. Both, read and write, channels use the same signals and naming convention (except a passthrough write_strobe signal).
write and read signals indicate a new request and kept high until *_done signal is set.*_done signals indicates that the operation will be completed at the next positive edge, same as AXI protocol.*_data signals contains the operation data.*_addrs signals contains the address for the operation.*_error signals indicate and error in the operation.GP_ADDR_WIDTH is used to determine the width of *_addrs signals.Write and read channels work independently. Interface passes signals at the same cycle as they are issued, and holds them until the handshake.
Last Simulation: 10 October 2021, with Vivado Simulator.
CERN Open Hardware Licence Version 2 - Weakly Reciprocal