Verilog code for scanning a four by four matrix keypad.
Verilog code for scanning and debouncing a four by four matrix keypad.
Implemented on an Altera Cyclone FPGA development board.
The key pad decoder module assumes a normal telephone layout plus an additional column for A - D.
1 2 3 A
4 5 6 B
7 8 9 C
* 0 # D
Each key has a 4-bit address of the form Col:Row.
Key | 1 | 2 | 3 | A | 4 | 5 | 6 | B |
---|---|---|---|---|---|---|---|---|
Address | 0000 | 0001 | 0010 | 0011 | 0100 | 0101 | 0110 | 0111 |
Additionally, it is assumed in the scanning (debouncing) module that the keys are normally disconnected and are pulled low when pressed (i.e. that they keyboard is not powered).
The keypad interpreter module has three outputs and one input,
Ouputs
Inputs
Below are issues that some folks have been kind enough to point out, I have not implimented them as I have no way to test and verify them.
On the decoder unit, the out variable is set to 7 bit lengths but only 4 bits are used.
It has been confired that the “waitbit” is needed. While I poorly (read: didn’t) document what it is for, I am told that it insures that keypresses are recognized at the right time. I’m sure testing with the variable always set high will reveal make it clear to anyone with a dev board and keypad.
Tested on Intel DK-DEV-4CGX150N, Artyv s7, and others.
If you have questions, concerns, or comments please feel free to contact me via
adam.a.nunez@gmail.com
Copyright (C) 2014 Adam Nunez
This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.
This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See theGNU General Public License for more details.