FPGA/ASIC BLOS-Projects 返回
项目作者： JiriS97

项目描述 ：
Working projects from BLOS lessons on Brno University of Technology
高级语言： VHDL
项目地址: git://github.com/JiriS97/BLOS-Projects.git
创建时间： 2017-10-18T18:56:34Z
项目社区：https://github.com/JiriS97/BLOS-Projects
开源协议：MIT License
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uloha_04A_1647921793650.pdf
uloha_05A_1647921798562.pdf
uloha_06A_1647921798709.pdf
uloha_07A_1647921798785.pdf
NEXYS3_sch_1647921788802.pdf
Nexys3_rm_1647921789043.pdf
uloha_01A_1647921789171.pdf
uloha_02A_1647921789216.pdf
uloha_03A_1647921789247.pdf
uloha_04A_1649867025055.pdf
uloha_05A_1649867025252.pdf
uloha_06A_1649867025451.pdf
uloha_07A_1649867025652.pdf
Nexys3_rm_1649867024050.pdf
uloha_01A_1649867024290.pdf
uloha_02A_1649867024468.pdf
uloha_03A_1649867024763.pdf
NEXYS3_sch_1649867023616.pdf