项目作者： mishal23

项目描述：
Automatic Door Controller built as a part of Mini Project for course CO202 - Design of Digital Systems

高级语言： Verilog

项目主页：

项目地址: git://github.com/mishal23/automatic-door-controller.git

创建时间： 2017-10-22T18:44:36Z
项目社区：https://github.com/mishal23/automatic-door-controller
开源协议：
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Automatic Door Controller

Mini Project done as a part of Course CO202
Please read the abstract for further information(It took us a while to write it, hope that doesn’t go in vain).
Circuit simulated in Logisim.
HDL used : Icarus Verilog.
Behavorial and DataFlow Modelling was coded in iverilog.

Abstract_1647939964693.pdf
Dataflow_1647939964749.pdf
Verilog coding instruction_1647939964954.pdf
Abstract_1650109137881.pdf
Dataflow_1650109138117.pdf
Verilog coding instruction_1650109138493.pdf