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项目作者： melzareix

项目描述 ：
Mips Pipeline Processor
高级语言： Verilog
项目地址: git://github.com/melzareix/mips-pipeline.git
创建时间： 2017-04-13T13:33:13Z
项目社区：https://github.com/melzareix/mips-pipeline
开源协议：MIT License
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Mips Processor with Pipeline

Verilog Code to simulate MIPS Processor with pipeline.

Developed as the course project for Computer Architecture Course @ German University in Cairo.

How to Run

1 - Download the verilog compiler http://iverilog.icarus.com/

2 - Clone this repo 

  1. git clone https://github.com/melzareix/mips-pipeline.git
  2. cd mips-pipeline

3 - Compile all the files

  1. iverilog -o main *.v

4 - Run the compiled binary

  1. vvp main