项目作者: russkel

项目描述 :
VCD to VGA frame viewer
高级语言: Python
项目地址: git://github.com/russkel/vcdvgaemu.git
创建时间: 2017-04-21T02:46:33Z
项目社区:https://github.com/russkel/vcdvgaemu

开源协议:

下载


This Python script draws VGA frames from a VCD dump (likely from Icarus Verilog).

It requires python 3, matplotlib, numpy and pyparsing libraries. (pip install matplotlib numpy pyparsing)

You need to modify (make a copy of) your test bench file and modify it so only the required signals are dumped, otherwise the resulting dump will be a few hundred megabyte dump. Large VCD files will take a long time for Python to parse:

  1. `timescale 1ns / 1ps
  2. module TB_yourproject;
  3. // Inputs
  4. // snip snip
  5. // Instantiate the Unit Under Test (UUT)
  6. yourproject uut (
  7. //snip snip
  8. );
  9. initial begin
  10. $dumpfile("vga_data.vcd");
  11. $dumpvars(0,
  12. uut.vga.vert_sync,
  13. uut.vga.horiz_sync,
  14. uut.image_generator.pixel_R,
  15. uut.image_generator.pixel_G,
  16. uut.image_generator.pixel_B
  17. );
  18. end
  19. initial begin: stopat
  20. #34000000; $finish; // 1x Vert scan = 416800 clocks * 40n = 16672000 ns
  21. end
  22. endmodule

Compile and run your modified test bench to generate the VGA signal only VCD.

You must specify the full path to the VSYNC, Red, Blue and Green variables when calling vcdvga.py. Using the above testbench as an example, noting that the VCD dump will be written to vga_data.vcd:

python3 vcdvga.py -V "TB_yourproject.uut.vga.vert_sync" -R "TB_yourproject.uut.image_generator.pixel_R" -G "TB_yourproject.uut.image_generator.pixel_G" -B "TB_yourproject.uut.image_generator.pixel_B" path/to/vga_data.vcd

And then the frame will draw to the screen.