FPGA/ASIC>> platform>> 返回
项目作者： LudwigCRON

项目描述 ：
digital platform of obvious block
高级语言： SystemVerilog
项目地址: git://github.com/LudwigCRON/platform.git
创建时间： 2020-08-02T22:53:04Z
项目社区：https://github.com/LudwigCRON/platform
开源协议：
下载


Digital Platform

the purpose of this platform is two folds:

  • make FPGA and system design easier
  • validate reflow at a bigger scale

digital blocks

internal bus

  • abus
  • ports
  • sram

basic

  • adder_cla
  • adder_rca
  • comp_eq
  • comp_gt
  • comp_lt
  • gray_counter
  • multiplier_booth_4
  • multiplier_comb
  • resync + clock mux

signal processing

  • fir
  • sinus
  • cosinus
  • viterbi decoder

tests

  • fcounter
  • jtag_sib
  • jtag_tdr
  • jtag_fsm
  • oscillator
  • timer

mixed-mode

  • adc_sar