项目描述 ：
This project makes one hardware-software co-design solution of chess engine accelerator. For design it is used VHDL, description of system SystemC and functional verification SystemVerilog

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项目地址: git://github.com/dejangrubisic/Hardware-acceleration-of-chess-engine.git

创建时间： 2018-06-26T17:27:13Z
项目社区：https://github.com/dejangrubisic/Hardware-acceleration-of-chess-engine
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