项目描述 ：
A Deep Neural Network-inference accelerator is created in hardware. The codes for hardware is written in System Verilog. The hardware module is interfaced with NIOS computer system, thus this hardware acts as a peripheral to the computer system. The driver code to interface the hardware is written in C. Speedup compard to software is 400 times.

高级语言： SystemVerilog

项目主页：

项目地址: git://github.com/sickRanchez-c137/InferenceInFPGA.git

创建时间： 2019-11-15T21:48:52Z
项目社区：https://github.com/sickRanchez-c137/InferenceInFPGA
开源协议：
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