Verilog and Qflow Design Verification

University of Costa Rica

Last updated: 2015-04-14

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This repository contains various projects focused on the verification, timing analysis, and power analysis of designs using Verilog and Qflow. All projects were conducted at the University of Costa Rica in August 2020.

Projects

1. Timing Design (Verilog)

This project involves the design and synthesis analysis of a counter. The goal is to visualize different aspects of timing in the behavioral description of the counter.

2. Functional Verification (Verilog)

This project focuses on the functional verification of three counters. The aim is to ensure the correct operation of the designs.

3. Power Analysis (Verilog)

This task involves analyzing the power consumption of three different adders. The goal is to understand the power dynamics of these designs.

4. Qflow Analysis (Qflow)

This project analyzes various aspects of designs using Qflow, including:

Frequency
Area
Number and type of gates
Path delays
Place and route

5. Complete Design Process (Verilog, Qflow, Electric, Spice)

This project involves the complete process of designing 4-bit and 32-bit counters. The aim is to ensure the correct operation of the designs.