• eSpiMasterBfm
  • Features
  • Releases
  • Example
  • File Listing
  • BFM procedures
  • FAQ
    • INIT ends with WAIT_ALERT
  • Contributors wanted
  • eSPI Slaves
  • References

eSpiMasterBfm

Enhanced SPI Master Bus Functional Model

Features

The eSpiMasterBfm provides VHDL procedures to interact with an eSPI endpoint.
Currently are procedures available for:

• IO Read/Write
• Memory Read/Write
• Endpoint Configuration

Releases

Example

The full provided function set demonstrates the eSpiMasterBfm_tb.vhd.
A tiny testbench example shows the snippet below:

library ieee;
  use ieee.std_logic_1164.all;
library work;
  use work.eSpiMasterBfm.all;
entity espi_tb is
end entity espi_tb;
architecture sim of espi_tb is
  -----------------------------
  -- ESPI ITF
  signal CSn    : std_logic;
  signal SCK    : std_logic;
  signal DIO    : std_logic_vector(3 downto 0);
  signal ALERTn : std_logic;
  signal RESETn : std_logic;
  -----------------------------
begin
  -----------------------------
  -- DUT
  --   add ESPI Slave here
  -----------------------------
  -----------------------------
  -- stimuli process
  p_stimuli : process
    variable eSpiBfm : tESpiBfm;                        -- eSPI Master bfm Handle
    variable good    : boolean := true;                 -- test state
    variable slv08   : std_logic_vector(7 downto 0);    -- help variable
  begin
    -- Initializes Endpoint according 'Exit G3' sequence
    --   init( this, RESETn, CSn, SCK, DIO, ALERTn, good, log );
    init( eSpiBfm, RESETn, CSn, SCK, DIO, ALERTn, good, INFO );
    -- write to io-mapped address
    --   IOWR( this, CSn, SCK, DIO, adr, data, good )
    IOWR( eSpiBfm, CSn, SCK, DIO, x"0080", x"47", good );   -- P80
    -- read from io-mapped address
    --   IORD( this, CSn, SCK, DIO, adr, data, good )
    IORD( eSpiBfm, CSn, SCK, DIO, x"0081", slv08, good );   -- P81
    -- write to memory-mapped address
    --   MEMWR32( this, CSn, SCK, DIO, adr, data, good );
    MEMWR32( eSpiBfm, CSn, SCK, DIO, x"00000080", x"47", good );    -- byte write
    -- read from memory-mapped address
    --   MEMRD32( this, CSn, SCK, DIO, adr, data, good );
    MEMRD32( eSpiBfm, CSn, SCK, DIO, x"00000080", slv08, good );    -- byte read
    -- done
    Report "That's it :-)";
    wait;   -- stop continuous run
  end process p_stimuli;
  -----------------------------
  -----------------------------
  -- External Pull Resistors
  SCK    <= 'L';
  DIO    <= (others => 'H');
  ALERTn <= 'H';
  -----------------------------
end architecture sim;

File Listing

The table below lists the major files in this project:

BFM procedures

FAQ

INIT ends with WAIT_ALERT

ESPI slave initialization INIT(bfm, RESETn, CSn, SCK, DIO, ALERTn, good) stops with the log message ** Note: eSpiMasterBfm:WAIT_ALERT.
This is caused by non asserting the two virtual wire inputs SLAVE_BOOT_LOAD_DONE=1 and SLAVE_BOOT_LOAD_STATUS=1. According the
eSPI Specification
chapter Exit from G3 point 8 needs both virtual wires set to logical one for exit G3.

Contributors wanted

If you think useful project and also helpful, feel free to fork and contribute.
The license does not require this, but the project will love it :-). Contributors welcome.

eSPI Slaves

• Intel/Altera eSPI to LPC Bridge Core

References

• Intel eSPI Specification