项目作者: plkpiotr
项目描述 :
Introduction to reconfigurable computing in Verilog [2018]
高级语言: Verilog
项目地址: git://github.com/plkpiotr/reconfigurable.git
Digital electronics classes from Zybo
Software stack
- Vivado 2017.4
- Visual Studio Code 1.22.2
Table of contents
01 - Diodes and switches:
02 - Cascade of AND gates:
03 - Counter modulo:
04 - Complex logical module:
05 - Delay line:
06 - Mysterious module:
- mysterious.v
- tb_mysterious.v
07 - State machine*:
- input.txt
- machine.v
- output.txt
- tb_machine.v
08 - Ready-made OR gate:
- lut.txt
- or_gate.m
- tb_or_gate.v
09 - Simple arithmetic:
- delay.v
- simple.v
- tb_simple.v
- tm_simple.m
The asterisk indicates that the module needs improvment or adding additional files.
License
MIT