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项目作者： cw1997

项目描述 ：
SDRAM Controller
高级语言： HTML
项目地址: git://github.com/cw1997/SDRAM-Controller.git
创建时间： 2021-04-29T13:11:33Z
项目社区：https://github.com/cw1997/SDRAM-Controller
开源协议：Apache License 2.0
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SDRAM-Controller

SDRAM Controller, written by SystemVerilogHDL, supporting passing parameters including CAS Latency(CL), burst mode enable and burst length, using writing and reading control signal as request/response handshake bus protocol