FPGA/ASIC Hardware-Neural-Network-Generator 返回
项目作者： ysabhi1993

项目描述 ：
Designed a Neural Network Generator using C++ and System Verilog
高级语言： C++
项目地址: git://github.com/ysabhi1993/Hardware-Neural-Network-Generator.git


Paper_review-1_1648047432899.docx
Paper_review-2_1648047432971.docx
Paper_review-3_1648047433029.docx
~$per_review-1_1648047433390.docx
New Microsoft Word Document_1648047434072.docx
1_taylor_landscape_ds_ieee_micro_2013_1648047432467.pdf
2_p40-bacon_1648047432615.pdf
Power_FPGAvsASIC_1648047433091.pdf
paper-rev-1(1)_1648047433190.pdf
paper-rev-2_1648047433240.pdf
syllabus-v2_1648047433289.pdf
Project1_report_1648047433518.pdf
ESE_507_Project2_Report_1648047433974.pdf
Project3_Report_1648047434150.pdf
proj3_1648047434744.pdf