项目作者： pulp-platform
项目描述 ：
Control interface for FLL
高级语言： SystemVerilog
项目地址: git://github.com/pulp-platform/apb_fll_if.git
APB FLL Interface
This unit acts as a bridge between an APB bus and the FLL interface that was
used for the FLL inside imperio, the first ASIC implementation of PULPino.
At the moment it supports up to two FLLs.
