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项目作者： tahaShm

项目描述 ：
This repo consists of 6 projects implemented with Verilog language, ModelSim environment, and Quartus.
高级语言： Verilog
项目地址: git://github.com/tahaShm/digital-logic-design.git
创建时间： 2021-08-27T11:11:34Z
项目社区：https://github.com/tahaShm/digital-logic-design
开源协议：
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Assignment 1 F97_1647870145420.pdf
CA1_810196491_explanations_1647870145508.pdf
Assignment 2 F97_1647870145631.pdf
CA2_explanation_1647870145721.pdf
Assignment 3 F97_1647870145775.pdf
Assignment 4 F97_1647870145893.pdf
Assignment 6 F97_1647870146226.pdf