python>> logic-design>> 返回
项目作者： HsuChiChen

项目描述 ：
sequence detector with overlapped 2 patterns 010111 or 1101
高级语言： Verilog
项目地址: git://github.com/HsuChiChen/logic-design.git
创建时间： 2021-08-24T07:13:50Z
项目社区：https://github.com/HsuChiChen/logic-design
开源协议：
下载


lab01_1647909543534.pdf
lab02_1647909543707.pdf
lab03_1647909543790.pdf
lab04_1647909543931.pdf
lab05_1647909544079.pdf
lab06_1647909544299.pdf
lab07_1647909544429.pdf
lab08_1647909544521.pdf
lab09_1647909544612.pdf
lab10_1647909544749.pdf
lab11_1647909544832.pdf
lab12_1647909544908.pdf
lab13_final_project_1647909544976.pdf