项目作者： Ayush9719

项目描述：
This consists of a simulation of direct mapping in cache using VHDL

高级语言： VHDL

项目主页：

项目地址: git://github.com/Ayush9719/Cache-Simulation-in-VHDL.git

创建时间： 2018-06-28T17:39:49Z
项目社区：https://github.com/Ayush9719/Cache-Simulation-in-VHDL
开源协议：
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Cache-Simulation-in-VHDL

This consists of a simulation of direct mapping in cache using VHDL

I have created a cache simulation using the VHDL and simulated the concept of direct Mapping and the Write-through policy using the created cache. ModelSim Simulator was used to simulate the VHDL code. Each block of cache consists of 8-bit word.