项目描述 ：
VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field-programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming language.

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项目地址: git://github.com/soumyadip007/VHDL-Modelsim-Altera-Simulator-COA.git

创建时间： 2019-04-17T18:27:18Z
项目社区：https://github.com/soumyadip007/VHDL-Modelsim-Altera-Simulator-COA
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