项目作者: abaelen

项目描述 :
Covers the DEEDS training material for electronic Design
高级语言: VHDL
项目地址: git://github.com/abaelen/FPGA-DEEDS-Training-Material.git
创建时间: 2020-12-28T17:04:47Z
项目社区:https://github.com/abaelen/FPGA-DEEDS-Training-Material

开源协议:MIT License

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FPGA - Electronic Design DEEDS Training Material

Covers the DEEDS training material for electronic Design

Electronic design application DEEDS allows to simulate and create electronic designs.
The application provides for a lot of training material starting with the basics and continues to actual FPGA design.
The application allows for VHDL creation immediate from the block design.

As such the application allows to:
1) learn basics of electronic design
2) simulate own designs
3) create VHDL files from design
4) learn the VHDL language for FPGA programming

The files kept here will cover:
1) the solutions for the training material
2) own designs and tried outs for FPGA programming (CORA Z6S board)

Requisites:
1) DEEDS application: https://www.digitalelectronicsdeeds.com/deeds.html
2) FPGA board is not required

Happy designing!