项目作者: aminrashidbeigi

项目描述 :
SAYEH cpu-memory basic computer
高级语言: VHDL
项目地址: git://github.com/aminrashidbeigi/SAYEH.git
创建时间: 2017-06-02T18:25:44Z
项目社区:https://github.com/aminrashidbeigi/SAYEH

开源协议:

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SAYEH
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This CPU exploits a 16-bit data-bus and also a 16-bit
address-bus. Instructions used in this processor has 8 or 16-bit width. Short instructions (8-bit
ones) contain shadow instructions, which effectively pack 2 such instructions (8-bit) into a single
16-bit word.

Overveiw
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Datapath
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Controller
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