项目作者: ShashankVM

项目描述 :
n-bit up-down binary counter and n-bit gray counter in SystemVerilog.
高级语言: SystemVerilog
项目地址: git://github.com/ShashankVM/generic_binary_and_gray_counter.git
创建时间: 2021-02-14T14:52:23Z
项目社区:https://github.com/ShashankVM/generic_binary_and_gray_counter

开源协议:BSD 3-Clause "New" or "Revised" License

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binary_counter

n-bit binary counter with asynchronous reset in SystemVerilog.

binary_to_gray

n-bit binary to gray code combinational converter circuit in SystemVerilog.

demultiplexer

Demultiplexer of parameterized width and parameterized number of output ports.

full_adder

n-bit full adder in SystemVerilog

full_subtractor

n-bit full subtractor in SystemVerilog

gray_counter

n-bit gray code counter with asynchronous reset implemented using binary counter and binary to gray code combinational converter circuit in SystemVerilog.

multiplexer

Multiplexer of parameterized width and parameterized number of input ports.